The present invention relates to a semiconductor integrated circuit device, particularly a technique which is effective in its application to a package for mounting a very high-speed LSI thereon.
High-speed LSIs, e.g. GaAs (gallium arsenic) LSI, are used in various fields, including the transmission field, and recently the processing speed thereof has been increasing. In particular, in the high-speed digital transmission field such as optical communication, the transmission speed is much higher than 1 [Gbit/s], and even a very high-speed LSI having a transmission speed of 10 [Gbit/s] is being put to practical use.
In designing a package for mounting a semiconductor chip with such very high-speed LSI formed thereon, it is an important subject how characteristic impedance matching of signal transmission lines in the interior of the package is to be taken. This is because if there occurs mismatching of a characteristic impedance of signal transmission lines at the time of transmission of a high-frequency signal, there occurs a transmission loss such as signal reflection or waveform distortion, thus making it impossible to obtain a good transmission characteristic.
As an example of a package which has attained such characteristic impedance matching, reference is here made to U.S. Pat. No. 4,751,482.
FIG. 20 is a logical block diagram showing an example of a circuitry incorporated in a very high-speed LSI. This circuitry is a multiplexing circuitry for timewise multiplexing and outputting parallel data signals of four bits. Data signals (D) inputted from input terminals Din1-Din4 are applied to flip-flop circuits 103 through data input buffers 102. After signal synchronization in the flip-flop circuits 103, the signals are multiplexed at every two bits in 2:1 multiplexing circuits 104 each constituted by a latch circuit and a selector circuit. Further, after clock synchronization performed by a flip-flop circuit 106, the multiplexed signal is outputted through an output buffer 107.
The frequency of the clock signal applied to the circuitry through a clock input buffer 101 is divided into two by means of divider circuits 108, 108, where the frequencies of the clocks are divided in 1/2 and 1/4, respectively. The 1/4 frequency clock is outputted to the exterior through an output buffer 110 to synchronize an external circuitry which is for outputting the input data signals. Further, a reset signal (R) for resetting the internal circuitry is taken in through an input buffer 109 and there is made phase adjustment between the internal clocks generated by the divider circuits 108.
In the above multiplexing circuitry, the data output and clock input portions are running at the highest speed. Therefore, it is important to constitute such signal input/output characteristics using a system having a satisfactory impedance matching.